1 dqp3 80 dqp2 10 vssq 71 vssq 19 dq26 62 dq7 2 dq17 79 dq16 11 vddq 70 vddq 20 vddq 61 vddq 3 dq18 78dq15 12 dq23 69 dq10 dq9 21 vssq 60 vssq 4 vddq 77 vddq 13 dq24 68 22 dq27 59 dq6 5 vssq 76 vssq 14 vdd 67 vss 23 dq28 58 dq5 6 dq1975 dq14 15 vdd 66 vdd 24 dq29 57 dq4 28 dq31 53 dq2 7 dq20 74 dq13 16 vdd 65 vdd 25 dq3056 dq3 29 dq32 52 dq1 8 dq21 73 dq12 17 vss 64 zz 26 vssq 55 vssq 30 dqp451 dqp1 9 dq2272dq11 18 dq25 63 dq8 27 vddq 54 vddq 100 pin lqfp 20 mm x 14 mm body 0.65 mm nominal pin pitch
deselect begin read begin write burst read burst write burst ds write burst burst read ds ds writeread read write burstburst read write write read dsds 256kx36 bit memory array control logic mux output register mode a[17:0] ce1#, ce2, ce2# we# cke# adv/ld# bw[4:1]# clk oe# dq[32:1] dqp[4:1] address control d d dq q q q d
-5 (200 mhz) -6 (166 mhz) -7r5 (133 mhz) symparameterminmaxminmaxminmaxunits tkehcke# hold0.50.50.5ns tkescke# setup1.31.51.7ns taahadv/ld# hold0.50.50.5ns taasadv/ld# setup1.31.51.7ns tahaddress hold0.50.50.5ns tasaddress setup1.31.51.7ns tcehchip enable hold0.50.50.5ns tceschip enable setup1.31.51.7ns tdhwrite data hold0.50.50.5ns tdswrite data setup1.31.51.7ns twswe#, bwx# setup1.31.51.7ns twhwe#, bwx# hold0.50.50.5ns tkcclock cycle567.5ns tkhclock high22.53ns tklclock low22.53ns tkqclock to output valid33.54.2ns tkqhzclock to output high-z1.52.91.53.11.53.8ns tkqlzclock to output low-z1.51.51.5ns tkqxclock to output invalid1.51.51.5ns toelzoe# to output low-z000ns toehzoe# to output high-z33.54.2ns toeqoe# to output valid33.54.2ns toeqxoe# to output invalid000ns tzzzz activation222tkc tzzrzz deactivation555tkc tzzhzzz to dq hi-z100100100tkc tzzlzzz to dq lo-z000tkc
read/write timing a1a2a3a4a5a6a7 wda1wda2wda2+1ra3ra4ra4+1wda5ra6 nop, stall, deselect timing a1a2a3a4a5 wda1ra2 ra3wda4 ra5
zz timing
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